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| STLC60133 XDSL LINE DRIVER PRELIMINARY DATA s s s LOW NOISE : 4nV/ H z HIGH PEAK OUTPUT CURRENT: 500 mA HIGH SPEED - 140MHz Gain Bandwidth - 30MHz Gain Flatness - 400 V/us Slew Rate s LOW POWER OPERATION - 5V to 15V Voltage Supply - 12.5 mA/Amp (typ) Supply current - Power reduced Current HTSSOP28 ORDERING NUMBER: STLC60133 Temperature Range: -40C to +85C s s s s LOW SINGLE TONE DISTORTION THERMAL AND OVERLOAD PROTECTION HTSSOP28 PACKAGE -40 TO +85C OPERATING RANGE Two digital pins (PWDN0 and PWDN1) allow the driver to work in full performance mode, in low-power mode or two intermediate bias states. The low-power mode biases the output stage in order to provide a low impedance at the amplifier outputs for back termination. The STLC60133 is designed optimizing bandwidth and distortion performances. For proper device operating it is necessary to work with a gain level greater than 15.6dB. Typical differential gain is normally +27dB, while typical common mode gain is 15.6dB DESCRIPTION The STLC60133 is a dual amplifier featuring a high slew rate and a large bandwidth optimized for XDSL applications. The device is available in a HTSSOP 28 pin package (4x9 mm) with an exposed leadframe. Thanks to its small package this line driver is suitable for high density ADSL line card. Figure 1. BLOCK DIAGRAM -VS Op1 +VS IN1N IN1P PWDN0 PWDN1 BIAS DGND IN2N IN2P LOGIC + OUT1 TH DETCT. + Op2 D00TL462A OUT2 October 2001 This is preliminary information on a new product now in development. Details are subject to change without notice. 1/9 STLC60133 PIN CONNECTION RES N.C. N.C. IN2P IN2N OUT2 +VS +VS OUT1 IN1N IN1P N.C N.C. N.C. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 D00TL463A 28 27 26 25 24 23 22 21 20 19 18 17 16 15 RES N.C. N.C. N.C. PWDN1 BIAS -VS -VS DGND N.C. PWDN0 N.C. N.C. N.C. ABSOLUTE MAXIMUM RATINGS Symbol VCC VSS Vid Vi Top Tstg Tj Parameter Positive Supply voltage (note1) Negative Supply voltage (note1) Differential Input Voltage (note2) Common mode Input Voltage Operating Free Air Temperature Range Storage temperature Junction temperature Value +16.5 -16.5 5 1 -40 to +85 -65 to +150 150 Unit V V V V C C C THERMAL DATA Symbol Rthj-amb Parameter Thermal resistance junction to ambient (note 3) Value 29 Unit C/W 2/9 STLC60133 OPERATING RANGE Symbol Top VCC VSS VDGND Vicm Parameter Operating Temperature Range Positive Supply voltage (note1) Negative Supply voltage (note1) Digital Ground level Common Mode Input Voltage Range Value -40 to 85 +5 to +15 -5 to -15 VSS+5 PIN DESCRIPTION N 2, 3, 12, 13, 14, 15, 16, 17, 19, 25, 26, 27 4 5 6 7, 8 9 10 11 14 18 21, 22 23 1, 28 Pin NC Not Connected Description IN2P IN2N OUT2 +Vs OUT1 IN1N IN1P PWDN1 PWDN0 -Vs BIAS RES Non Inverting Input of Op. Amplifier 2 Inverting Input of Op. Amplifier 2 Ouput of Op. Amplifier 2 Positive Supply Voltage Ouput of Op. Amplifier 1 Inverting Input of Op. Amplifier 1 Non Inverting Input of Op. Amplifier 1 Power Down 1 logic input Power Down 0 logic input Negative Supply Voltage Bias Control pin To be left not connected Power Down Management The STLC60133 provides several quiescent bias levels from full performance, to reduced bias (in three steps through PWDN0/1 pins) or to full OFF operation (through BIAS pin). According to the different XDSL application (both site CO and CPE), different bias levels can be chosen maintaining good MTPR performances. In the following table are shown the bias levels versus the PWDN values. PWDN1 1 1 0 0 X PWDN0 1 0 1 0 X 100% 60% 40% 25% (low Zout but not OFF) Full OFF (High Zout via 250uA pulled out of BIAS pin) Bias Level 3/9 STLC60133 The bias level is programmed by the TTL logic level applied to the PWDN pins. The DGND pin is the logic ground reference for the PWDN pins. For normal operation the BIAS pin shall be left open. The BIAS control pin can be used to adjust the internal biasing and thus the quiescent current. By pulling out a current of 0A to 200A, the quiescent current can be adjusted from 100% (full ON) to a full OFF condition. However, considering the internal parameter spread to full shutdown the STLC60133 is recommended to pull down a 250A current from the BIAS pin. In the following figure is shown an implementation of a complete amplifier shutdown. To partially reduce the internal biasing also the PWDN pins can be used. Figure 2. Logic drive of bias pin for complete Amplifier Shutdown. 3.3V R2 50K R1 BIAS R1 = 47K for 12V R1 = 22K for 6V STLC60133 D01TL492 THERMAL SHUTDOWN A thermal protection is embedded in the STLC60133. In case of thermal overload the device is shut down at 160C and returns to normal operation when the temperature becomes lower than 145C. During the thermal shutdown the voltage at the BIAS pin goes to the DGND rail; when the device returns to the normal operation the voltage at the BIAS pin goes to the positive rail. In this condition the BIAS pin can be used as thermal overload indicator. MAXIMUM POWER DISSIPATION Maximum Junction Temperature allowed for proper device operation is T j = 140C. A Typical Thermal Resistance Junction to ambient of 29C/W can be obtained mounting the device on a 4 layer board whithin 10 square inches of copper and having the exposed pad contacting a proper copper area . It shall be noted that the exposed pad of the device is electrically connected to the VSS negative supply. Figure 3. Shutdown and alarm circuit VCC 200A 10K SHUT DOWN BIAS VEE PWDN0 PWDN1 +5V 10K OR ALARM BIAS 100K 1/4 HCF40109B ST D01TL491 STLC60133 VBIAS=VCC -1.5V BIAS OR 0-200A VCC +5V 10K BIAS 1M ALARM MIN 350 4/9 STLC60133 ELECTRICAL CHARACTERISTCS Test Conditions: (VCC = 12V , Tamb = 0 to 70C , Single amplifier in normal condition (PWDN0 = 1, PWDN1 = 1), unless otherwise specified). The limits listed below are guaranted in the above temperature range (0-70C) by specific testing at different temperature or by product characterisation. TRANSMISSION PATH Symbol SR GBW THD Slew Rate Gain Bandwidth Single ended Distortion Parameter Test Condition G = 6, Vout = 2Vpp G = 6, Vout = 2Vpp, f = 5MHz G = 6, f = 1MHz, Vout = 12Vpp, Rl = 16.5 Rl = 100 G = 6, f = 1MHz, Vout = 24Vpp, Rl = 33 Rl = 100 G = 6, Vout = 3Vp each tone, f = 500KHz, f = 10KHz Rl = 16.5 Rl = 100 G = 6, Vout = 6Vp each tone, f = 500KHz, f = 10KHz Rl = 33 Rl = 100 90 -40 -45 -50 -55 Min. Typ. 400 140 -47 -52 Max. Unit V/us MHz dBc DTHD Differential THD (2) dBc IMD Single ended IMD -54 -60 -70 -75 dBc DIMD Differential IMD (2) -66 -72 5 dBc A 2 4 10 6 nV/ Hz mV V dB +10.8 600 1000 12 8 5 4 1.5 1400 16.2 10.7 7.5 5.3 2.0 V mA mA mA/Amp IB OZ VN IOV ICMR CMRR OVS LOC SCC QC Input Biasing Output Impedance Voltage Noise (RTI) Input Offset Voltage Input Common Mode Voltage Range Common Mode Rejection Ratio Output Voltage Swing Linear Output Current Short Circuit Current (1) Quiescent Current f = 1 MHz f = 1 MHz, Vin = 100mV Single ended, Rl = 100, G = 6 Single ended, Rl = 10, G = 6 Single ended PWDN1, PWDN1, PWDN1, PWDN1, PWDN0 = 1,1 PWDN0 = 1,0 PWDN0 = 0,1 PWDN0 = 0,0 -10.8 400 -1 PWDN0 = PWDN1 = 0; f = 1MHz f = 30KHz +1 40 SC PSRR BIASV DCG Shutdown Current Power Supply Rejection ratio Bias Pin Voltage DC Gain 250A out of Bias pin f = 500kHz, V = 100mV 30 10 mA/Amp dB 10.5 80 V dB Notes: 1. The output stage of the STLC60133 is designed for maximum load current capability. As a result, shorting the output to common can cause the STLC60133 to source or sink 1.4A. 2. Guaranteed by product characterization. 5/9 STLC60133 ELECTRICAL CHARACTERISTICS Test conditions (V CC = 6V, Tamb = 0 to 70C ,Single amplifier in normal condition (PWDN0 = 1, PWDN1 = 1), unless otherwise specified.) The limits listed below are guaranted in the above temperature range by (0-70C) specific testing at different temperature or by product characterisation. TRANSMISSION PATH Symbol SR GBW THD Slew Rate Gain Bandwidth Single Ended Distortion Parameter Test Condition G = 6, Vout = 2Vpp G = 6, Vout = 2Vpp, f = 5MHz G = 6, f = 1MHz, Vout = 6Vpp, Rl = 25 Rl = 100 G = 6, f = 1MHz, Vout = 12Vpp, Rl = 25 Rl = 100 G = 6, Vout = 1.5Vp each tone, f = 500KHz, f = 10KHz Rl = 25 Rl = 100 G = 6, Vout = 3Vp each tone, f = 500KHz, f = 10KHz Rl = 25 Rl = 100 90 -40 -45 -50 -55 Min. Typ. 400 140 -46 -51 Max. Unit V/us MHz dBc DTHD Differential THD (2) dBc IMD Single Ended IMD -65 -70 -76 -81 dBc DIMD Differential IMD (2) -77 -82 5 dBc A 10 6 nV/ Hz mV V dB +5 420 1000 1400 13.7 9 6.5 4.5 2.0 V mA mA mA/Amp IB VN IOV ICMR CMRR OVS LOC SCC QC Input Biasing Voltage Noise (RTI) Input Offset Voltage Input Common Mode Voltage Range Common Mode Rejection Ratio Output Voltage Swing Linear Output Current Short Circuit Current (1) Quiescent Current f = 1 MHz f = 1 MHz, Vin = 100mV Single ended, Rl = 100, G=6 Single ended, Rl = 10, G=6 Single ended, PWDN1, PWDN0 = PWDN1, PWDN0 = PWDN1, PWDN0 = PWDN1, PWDN0 = 1,1 1,0 0,1 0,0 -5 300 -1 f = 30KHz 4 +1 40 10 7 5 3.5 1.5 30 4 40 4.5 80 SC PSRR BIASV DCG Shutdown Current Power Supply Rejection ratio Bias Pin Voltage DC Gain 250A out of Bias pin f = 500kHz, V = 100mV mA/Amp dB V dB Notes: 1. The output stage of the STLC60133 is designed for maximum load current capability. As a result, shorting the output to common can cause the STLC60133 to source or sink 1.4A. 2. Guaranteed by product characterization. 6/9 STLC60133 DIGITAL INTERFACE (PWDN0, PWDN1, Vcc = 12 V or 6 V) Symbol Vil Vih Parameter Input low voltage Input high voltage Test Condition Min. 0 2.2 Typ. Max. 0.8 5.5 Unit V V THERMAL PROTECTION Symbol Thsd Thist Parameter Thermal shut down threshold Thermal detector histeresys Test Condition Min. Typ. 160 15 Max. Unit C C Figure 4. Single ended Test Circuit G = 6 200 VIN + +VS 0.1F 10F RL 1200 VOUT 0.1F D00TL464 10F -VS Figure 5. Differential Test Circuit G = 6 10F +VS 200 + 1200 1200 0.1F +VOUT VIN 200 RL + 0.1F -VOUT -VS 10F D00TL465A 7/9 STLC60133 mm DIM. MIN. A A1 A2 b c D (*) D1 E E1 (*) E2 e L L1 k aaa 0.1 0.45 6.2 4.3 0.8 0.19 0.09 9.6 9.7 5.5 6.4 4.4 3.0 0.65 0.6 1.0 0 (min), 8 (max) 0.004 0.75 0.018 6.6 4.5 0.244 0.169 1.0 TYP. MAX. 1.2 0.15 1.05 0.3 0.2 9.8 0.031 0.007 0.003 0.377 0.382 0.216 0.252 0.173 0.118 0.026 0.024 0.039 0.029 0.260 0.177 0.039 MIN. TYP. MAX. 0.0 0.006 0.041 0.012 0.008 0.385 inch OUTLINE AND MECHANICAL DATA (*) Dimensions D and E1 does not include mold flash or protusions. Mold flash or protusions shall not exceed 0.15mm per side. HTSSOP28 (Exposed Pad) A2 A1 A c E1 aaa C b e D D1 SEATING PLANE 1 1 4 E2 E L L1 HTSSO28M 0.25mm 0.10inch GAUGE PLANE C k 28 15 8/9 STLC60133 Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics (R) 2001 STMicroelectronics - All Rights Reserved STMicroelectronics GROUP OF COMPANIES Australia - Brazil - China - Finland - France - Germany - Hong Kong - India - Italy - Japan - Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - U.S.A. http://www.st.com 9/9 |
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